Full adder truth table, circuit, k map & its implementation

In this article we will going to learn about full adder truth table and then drive its k map to form its equation. After this we will reduce the equation, so that we can implement full adder using XOR gate. We will also see how to make full adder using half adder.

What is Full Adder

A Full adder is a combinational ciruit that performs the sum of three bits. It includes two significant bits and one carry bits.

full adder truth table

carry bit
000 000
100 110
201 010
301 101
410 010
510 101
611 001
711 111
Full Adder Truth Table
  • When both inputs are low then sum and carry outputs will be logic low or 0.
  • If any one input is high then sum will be logic high (1) and carry out will be logic low (0).
  • When two inputs are high then sum becomes logic low (0) and carry out will be logic high (1).
  • And if all inputs are high(1) then the output sum and carry will be logic high (1).

Karnaugh map of full adder

Full Adder Truth table
Figure: K Map of Full Adder

Full Adder equation & its reduction to XOR logic form

Full Adder Sum equation

Sum = X’ Y Z’ + X Y’ Z’ + X’ Y’ Z + X Y Z

= Z’ ( X’ Y + X Y’ ) + Z( X’ Y’ + X Y )

= X xor Y xor Z

Carry = X Z + X Y + Y Z

or Carry = Z ( X Y’ + X’ Y) + X Y

= Z X Y’ + Z X’ Y + X Y ( note: we can verify these equation by using truth table)

Full adder implementation using XOR gate And/Or Half Adder

Full adder truth table
Figure: Full Adder using half adder or xor gate.

Full Adder VHDL code

library IEEE;
use IEEE.std_logic_1164.all;

entity Fulladder is
port (x : in std_logic;
y : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout :out std_logic);
end Fulladder;

architecture fa of Fulladder is
sum <= (x xor y) xor cin;
cout <= (x and y) or (cin and x) or (cin and y);
end fa;

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